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Timing-Driven Global Routing with Efficient Buffer Insertion Jingyu XU Xianlong HONG Tong JING Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E88-A No.11 pp.3188-3195 Publication Date: 2005/11/01 Online ISSN: DOI: 10.1093/ietfec/e88-a.11.3188 Print ISSN: 0916-8508 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: VLSI layout, global routing, timing-driven, buffer insertion, routability, Full Text: PDF(220.3KB)>>
Summary: Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becomes inadequate. In this paper, we present an efficient timing-driven global routing algorithm with buffer insertion. Our approach is capable of applying topological-based timing optimization and buffer insertion simultaneously with routablity considerations. Compared with previous works, we efficiently solve the timing issues under a limited buffer usage. The experimental results have demonstrated significant delay improvement within short runtime with very small number of buffers inserted. | ||||||||||
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