Summary
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Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model Hidenari NAKASHIMA Junpei INOUE Kenichi OKADA Kazuya MASU Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E88-A No.12 pp.3358-3366 Publication Date: 2005/12/01 Online ISSN: DOI: 10.1093/ietfec/e88-a.12.3358 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: interconnect, layout compaction, physical design, placement, core utilization, Full Text: PDF(2MB)>>
Summary: Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models. | ||||||||||
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