IEICE Trans - Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization

Tetsuya IIZUKA
Makoto IKEDA
Kunihiro ASADA

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E88-A No.7 pp.1957-1963
Publication Date: 2005/07/01
Online ISSN:
DOI: 10.1093/ietfec/e88-a.7.1957
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword:
comprehensive cell layout synthesis, CMOS logic cell, critical area, defect sensitivity, yield optimization,

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Summary:
This paper proposes a cell layout synthesis technique to minimize the sensitivity to wiring faults due to spot defects. We modeled the sensitivity to faults on intra-cell routings with consideration to the spot defects size distribution and the end effect of critical areas. The effect of the sensitivity reduction on the yield is also discussed. By using the model as a cost function, we comprehensively generate the minimum width layout of CMOS logic cells and select the optimal layouts. Experimental results show that our technique reduces about 15% of the fault sensitivities compared with the wire-length-minimum layouts for benchmark CMOS logic circuits which have up to 14 transistors.

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