Summary
|
For Full-Text PDF, please login, if you are a member of IEICE, or go to Pay Per View on menu list, if you are a nonmember of IEICE. |
|
A Fast Delay Computation for the Hybrid Structured Clock Network Yi ZOU Yici CAI Qiang ZHOU Xianlong HONG Sheldon X.-D. TAN Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E88-A No.7 pp.1964-1970 Publication Date: 2005/07/01 Online ISSN: DOI: 10.1093/ietfec/e88-a.7.1964 Print ISSN: 0916-8508 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: clock networks, simulation, analysis, delay, Elmore delay, Full Text: PDF(627.6KB)>>
Summary: This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylov-subspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper selection of the simulation time step and interval based on Elmore delays, the delay of the clock signal between the clock source and the sink node as well as the clock skews between the sink nodes can be computed efficiently and accurately. Our experimental results show that the proposed algorithm is two orders of magnitude faster than HSPICE without loss of accuracy and stability. The maximum error is within 0.4% of the exact delay time. | ||||||||||
| ||||||||||
