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Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation Toshiki KANAMOTO Shigekiyo AKUTSU Tamiyo NAKABAYASHI Takahiro ICHINOMIYA Koutaro HACHIYA Atsushi KUROKAWA Hiroshi ISHIKAWA Sakae MUROMOTO Hiroyuki KOBAYASHI Masanori HASHIMOTO Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E89-A No.12 pp.3666-3670 Publication Date: 2006/12/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e89-a.12.3666 Print ISSN: 0916-8508 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: interconnect, delay variation, parasitic capacitance, SoC, Full Text: PDF(433.5KB)>>
Summary: In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today's SoC design flows. Most of the extraction programs use pattern-matching methods which introduces an improvable error factor due to the pattern interpolation, and an intrinsically inescapable error factor from the difference of boundary conditions in the electro-magnetic field solver. Here, we study impact of the intrinsic error on timing and crosstalk noise estimation. We experimentally show that the resulting delay and noise estimation errors show a scatter which is normally distributed. Values of the standard deviations will help designers consider the intrinsic error compared with other variation factors. | ||||||||||
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