Coding Floorplans with Fewer Bits

Katsuhisa YAMANAKA
Shin-ichi NAKANO

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E89-A    No.5    pp.1181-1185
Publication Date: 2006/05/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.5.1181
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graphs,  algorithms,  

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Summary: 
A naive coding of floorplans needs 2m bits for each floorplan. In this paper we give a new simple coding of floorplans, which needs only 5m/3 bits for each floorplan.

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