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A New Energy  Delay-Aware Flip-FlopInhwa JUNG Moo-young KIM Dongsuk SHIN Seon Wook KIM Chulwoo KIM Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E89-A No.6 pp.1552-1557 Publication Date: 2006/06/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e89-a.6.1552 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005)) Category: Keyword: flip-flop, pulsed-latch, low-power, high-speed, Full Text: PDF(754KB)>>
Summary: This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces E D by 45.5% over ep-SFF. The simulations were performed in a 0.1 µm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency. | ||||||||||
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