IEICE Trans - Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level

Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level

Daisuke SUZUKI
Minoru SAEKI
Tetsuya ICHIKAWA

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E90-A No.1 pp.160-168
Publication Date: 2007/01/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e90-a.1.160
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Side Channel Attacks
Keyword:
side-channel attacks, differential power analysis, hardware countermeasure, second-order DPA random switching logic, CMOS logic circuit,

Full Text: PDF(737.1KB)>>

Summary:
This paper proposes a new countermeasure, Random Switching Logic (RSL), against DPA (Differential Power Analysis) and Second-Order DPA at the logic level. RSL makes a signal transition uniform at each gate and suppresses the propagation of glitch to allow power consumption to be independent of predictable data. Furthermore, we implement basic logic circuits on the FPGA (Field Programmable Gate Array) by using RSL, and evaluate the effectiveness. As a result, we confirm the fact that the secure circuit can be structured against DPA and Second-Order DPA.

open access publishing via