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Modeling and Simulation of ΔΣ Fractional-N PLL Frequency Synthesizer in Verilog-AMS Zhipeng YE Wenbin CHEN Michael Peter KENNEDY Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E90-A No.10 pp.2141-2147 Publication Date: 2007/10/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e90-a.10.2141 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Nonlinear Circuits Keyword: fractional-N frequency synthesizer, delta-sigma modulator, modeling, simulation, sequence length, Full Text: PDF(2.1MB)>>
Summary: A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the ΔΣ modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the ΔΣ modulator. The spur-minimizing effect of an odd initial condition on the first accumulator of the ΔΣ modulator is verified. Sequence length control and its effect on the fractional-N frequency synthesizer are also discussed. The simulated results are in agreement with prior published data on fractional-N synthesizers and with new measurement results. | ||||||||||
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