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Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Yusuke IGUCHI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E90-A No.12 pp.2695-2702 Publication Date: 2007/12/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e90-a.12.2695 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Memory Design and Test Keyword: 6T SRAM cell, 8T SRAM cell, Vth variation, Full Text: PDF(1.7MB)>>
Summary: This paper compares areas between a 6T and 8T SRAM cells, in a dual-Vdd scheme and a dynamic voltage scaling (DVS) scheme. In the dual-Vdd scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology nodes all down to 32 nm. In contrast, in the DVS scheme, the 8T cell will becomes superior to the 6T cell after the 32-nm node, in terms of the area. | ||||||||||
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