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A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS Takeshi UENO Takafumi YAMAJI Tetsuro ITAKURA Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E90-A No.2 pp.365-371 Publication Date: 2007/02/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e90-a.2.365 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: D/A converter, current steering, low voltage, parasitic resistance, tree structure, Full Text: PDF(702KB)>>
Summary: This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth. | ||||||||||
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