Summary
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Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis Eui-Young CHUNG Hyuk-Jun LEE Sung Woo CHUNG Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E90-A No.4 pp.875-878 Publication Date: 2007/04/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e90-a.4.875 Print ISSN: 0916-8508 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: bus functional model, bus, stochastic, performance, inter-play, Full Text: PDF(157.6KB)>>
Summary: We present a scenario-aware bus functional modeling method which improves the accuracy of traditional methods without sacrificing the simulation run time. Existing methods focused on the behavior of individual IP (Intellectual Property) components and neglected the interplay effects among them, resulting in accuracy degradation from the system perspective. On the other hand, our method thoroughly considers such effects and increases the analysis accuracy by adopting control signal modeling and hierarchical stochastic modeling. Furthermore, our method minimizes the additional design time by reusing the simulation results of each IP component and an automated design flow. The experimental results show that the accuracy of our method is over 90% of RTL simulation in a multimedia SoC (System-on-Chip) design. | ||||||||||
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