A Block-Based Architecture for Lifting Scheme Discrete Wavelet Transform

Chung-Hsien YANG
Jia-Ching WANG
Jhing-Fa WANG
Chi-Wei CHANG

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E90-A    No.5    pp.1062-1071
Publication Date: 2007/05/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e90-a.5.1062
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Image
Keyword: 
discrete wavelet transform,  JPEG2000,  lifting scheme,  line-based DWT,  VLSI,  

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Summary: 
Two-dimensional discrete wavelet transform (DWT) for processing image is conventionally designed by line-based architectures, which are simple and have low complexity. However, they suffer from two main shortcomings - the memory required for storing intermediate data and the long latency of computing wavelet coefficients. This work presents a new block-based architecture for computing lifting-based 2-D DWT coefficients. This architecture yields a significantly lower buffer size. Additionally, the latency is reduced from N2 down to 3N as compared to the line-based architectures. The proposed architecture supports the JPEG2000 default filters and has been realized in ARM-based ALTERA EPXA10 Development Board at a frequency of 44.33 MHz.

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