Impact of Well Edge Proximity Effect on Timing

Toshiki KANAMOTO; Yasuhiro OGASAHARA; Keiko NATSUME; Kenji YAMAGUCHI; Hiroyuki AMISHIRO; Tetsuya WATANABE; Masanori HASHIMOTO

doi:10.1093/ietfec/e91-a.12.3461

Special Section on VLSI Design and CAD Algorithms

Impact of Well Edge Proximity Effect on Timing

Toshiki KANAMOTO, Yasuhiro OGASAHARA, Keiko NATSUME, Kenji YAMAGUCHI, Hiroyuki AMISHIRO, Tetsuya WATANABE, Masanori HASHIMOTO

Author information

Keywords: well edge proximity effect, WPE, delay, timing

JOURNAL RESTRICTED ACCESS

2008 Volume E91.A Issue 12 Pages 3461-3464

DOI https://doi.org/10.1093/ietfec/e91-a.12.3461

Details

Abstract

This paper studies impact of well edge proximity effect on circuit delay, based on model parameters extracted from test structures in an industrial 65nm wafer process. Experimental results show that up to 10% of delay increase arises by the well edge proximity effect in the 65nm technology, and it depends on interconnect length. Furthermore, due to asymmetric increase in pMOS and nMOS threshold voltages, delay may decrease in spite of the threshold voltage increase. From these results, we conclude that considering WPE is indispensable to cell characterization in the 65nm technology.

Corresponding author

Register with J-STAGE for free!