Special Section on Analog Circuit Techniques and Related Topics
A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals
2008 Volume E91.A Issue 2 Pages 557-560
Details
2008 Volume E91.A Issue 2 Pages 557-560
Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). In this letter, a low-power low-noise clock signal generator for ADCs is described. As a clock signal generator, a ring-VCO-based charge pump PLL is used to reduce power dissipation within a given jitter specification. The clock signal generator is fabricated on a CMOS chip with 200-MSPS 10-bit ADC. The measured results show that the ADC keeps a 60-MHz input bandwidth and 53-dB dynamic range and a next-generation mobile wireless terminal can be realized with the ADCs and the on-chip low-power clock generator.
