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Scan Design for Two-Pattern Test without Extra Latches Kazuteru NAMBA Hideo ITO Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.12 pp.2777-2785 Publication Date: 2005/12/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.12.2777 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Dependable Computing Keyword: two-pattern testing, delay fault testing, scan design, enhanced scan, Full Text: PDF(1.5MB)>>
Summary: There are three well-known approaches to using scan design to apply two-pattern testing: broadside testing (functional justification), skewed-load testing and enhanced scan testing. The broadside and skewed-load testing use the standard scan design, and thus the area overheads are not high. However fault coverage is low. The enhanced scan testing uses the enhanced scan design. The design uses extra latches, and allows scan-in any two-pattern testing. While this method achieves high fault coverage, it causes high area overhead because of extra latches. This paper presents a new scan design where two-pattern testing with high fault coverage can be performed with area overhead as low as the standard scan design. The proposed scan-FFs are based on master-slave FFs. The input of each scan-FF is connected to the output of the master latch and not the slave latch of the previous FF. Every scan-FF maintains the output value during scan-shift operations. | ||||||||||
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