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Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core Gang ZENG Hideo ITO Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.5 pp.984-992 Publication Date: 2005/05/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.5.984 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Dependable Computing Keyword: hybrid pattern BIST, core testing, test cost reduction, FPGA core, reconfigurable system-on-a-chip, Full Text: PDF(326.5KB)>>
Summary: In the Reconfigurable System-On-a-Chip (RSOC), an FPGA core is embedded to improve the design flexibility of SOC. In this paper, we demonstrate that the embedded FPGA core is also feasible for use in implementing the proposed hybrid pattern Built-In Self-Test (BIST) in order to reduce the test cost of SOC. The hybrid pattern BIST, which combines Linear Feedback Shift Register (LFSR) with the proposed on-chip Deterministic Test Pattern Generator (DTPG), can achieve not only complete Fault Coverage (FC) but also minimum test sequence by applying a selective number of pseudorandom patterns. Furthermore, the hybrid pattern BIST is designed under the resource constraint of target FPGA core so that it can be implemented on any size of FPGA core and take full advantage of the target FPGA resource to reduce test cost. Moreover, the reconfigurable core-based approach has minimum hardware overhead since the FPGA core can be reconfigured as normal mission logic after testing such that it eliminates the hardware overhead of BIST logic. Experimental results for ISCAS 89 benchmarks and a platform FPGA chip have proven the efficiency of the proposed approach. | ||||||||||
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