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Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.6 pp.1210-1216 Publication Date: 2005/06/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.6.1210 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Dependable Computing Keyword: BIST, fault coverage, defect level, Full Text: PDF(629.9KB)>>
Summary: Built-in self-test (BIST) hardware is included today in many chips. This hardware is used to test the chip's functional circuits. Since this BIST hardware is manufactured using the same technology as the functional circuits themselves, it is possible for it to be faulty. It is important, therefore, to assess the impact of this unreliable BIST on the product defect level after test. Williams and Brown's formula, relating the product defect level as a function of the manufacturing yield and fault coverage, is re-examined in this paper. In particular, special attention is given to the influence of an unreliable BIST on this relationship. We show that when the BIST hardware is used to screen the functional product, an unreliable BIST circuitry tends, in many cases, to reduce the effective fault coverage and increase the corresponding product defect level. The BIST unreliability impact is assessed for both early life phase, and product maturity phase. | ||||||||||
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