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Performance Evaluation of the AV CODEC on a Low-Power SPXK5SC DSP Core Takahiro KUMURA Norio KAYAMA Shinichi SHIONOYA Kazuo KUMAGIRI Takao KUSANO Makoto YOSHIDA Masao IKEKAWA Ichiro KURODA Takao NISHITANI Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.6 pp.1224-1230 Publication Date: 2005/06/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.6.1224 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Image Processing and Video Processing Keyword: MPEG-4, DSP, VLIW, low-power, Full Text: PDF(847KB)>>
Summary: This paper provides a performance evaluation of our audio and video CODEC by using a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXK5SC DSP cores. The SPXK5SC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to evaluate the overall performance of target LSIs on real workloads before actual LSI fabrication, software simulators are too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSIs integrated with a SPXK5SC DSP core in order to evaluate the overall performance of audio/video CODEC on a target system. Our emulation system using a DSP core TEG, which has a bus interface, and an FPGA is suitable for overall system evaluation on real-time workloads as well as architectural investigation. In this paper, we discuss the use of the emulation system in evaluating performance during AV CODEC execution. In addition, an architecture design based on our emulation system is also described. | ||||||||||
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