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Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access Masanori HARIYAMA Haruka SASAKI Michitaka KAMEYAMA Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.7 pp.1486-1491 Publication Date: 2005/07/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.7.1486 Print ISSN: 0916-8532 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Digital Circuits and Computer Arithmetic Keyword: stereo vision, SAD (sum of absolute differences), memory allocation, logic-in-memory architecture, Full Text: PDF(1.1MB)>>
Summary: This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions. | ||||||||||
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