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Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths Zhiqiang YOU Ken'ichi YAMAGUCHI Michiko INOUE Jacob SAVIR Hideo FUJIWARA Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.8 pp.1940-1947 Publication Date: 2005/08/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.8.1940 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Dependable Computing Keyword: design for testability, RTL data path, built-in self-test, low power testing, test scheduling, Full Text: PDF(447.5KB)>>
Summary: This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve low hardware overheads. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm the good performance and practicality of our new approaches. | ||||||||||
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