Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation

Kazuteru NAMBA
Hideo ITO

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E88-D    No.9    pp.2135-2142
Publication Date: 2005/09/01
Online ISSN: 
DOI: 10.1093/ietisy/e88-d.9.2135
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword: 
two-pattern testing,  adjacency test,  deterministic test generation,  BIST,  

Full Text: PDF(264.3KB)>>
Buy this Article


Summary: 
In delay fault BIST (Built-In-Self-Test), an adjacency test pattern generation scheme effectively generates robust test patterns. The traditional adjacency test pattern generation schemes use LFSR to generate first patterns, and thus they cannot generate test patterns for circuits with more than 30 inputs with high fault coverage in a practical amount of time. This paper proposes a deterministic delay fault BIST method using adjacency test pattern generation. The proposed scheme uses first patterns generated by a deterministic algorithm based on the analysis of independent partial circuits on the circuit under test. Experiments show that test patterns generated by the proposed method have both high fault coverage and short test length, resulting in a short test time.

open access publishing via