Effect of BIST Pretest on IC Defect Level

Yoshiyuki NAKAMURA
Jacob SAVIR
Hideo FUJIWARA

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E89-D    No.10    pp.2626-2636
Publication Date: 2006/10/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e89-d.10.2626
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword: 
BIST,  fault coverage,  defect level,  

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Summary: 
In [1] the impact of BIST on the chip defect level after test has been addressed. It was assumed in [1] that no measures are taken to ensure that the BIST circuitry is fault-free before launching the functional test. In this paper we assume that a BIST pretest is first conducted in order to get rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when it may be worthwhile to perform it.

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