Summary
|
For Full-Text PDF, please login, if you are a member of IEICE, or go to Pay Per View on menu list, if you are a nonmember of IEICE. |
|
Proposal of Testable Multi-Context FPGA Architecture Kazuteru NAMBA Hideo ITO Publication IEICE TRANSACTIONS on Information and Systems Vol.E89-D No.5 pp.1687-1693 Publication Date: 2006/05/01 Online ISSN: 1745-1361 DOI: 10.1093/ietisy/e89-d.5.1687 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Dependable Computing Keyword: multi-context FPGA, single stuck-at fault, design for testability, Full Text: PDF(412.9KB)>>
Summary: Multi-context FPGAs allow very quick reconfiguration by storing multiple configuration data at the same time. While testing for FPGAs with single-context memories has already been studied by many researchers, testing for multi-context FPGAs has not been proposed yet. This paper presents an architecture of testable multi-context FPGAs. In the proposed multi-context FPGA, configuration data stored in a context can be copied into another context. This paper also shows testing of the proposed multi-context FPGA. The proposed testing uses the testing for the traditional FPGAs with single-context. The testing is capable of detecting single stuck-at faults and single open faults which affect normal operations. The number of test configurations for the proposed testing is at most two more than that for the testing of FPGAs with single-context memories. The area overhead of the proposed architecture is 7% and 4% of the area of a multi-context FPGA without the proposed architecture when the number of contexts in a configuration memory is 8 and 16, respectively. | ||||||||||
| ||||||||||
