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Ricardo Jasinski, Fault-Tolerance Techniques for SRAM-Based FPGAs, The Computer Journal, Volume 50, Issue 2, March 2007, Page 248, https://doi.org/10.1093/comjnl/bxl060
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Today's SRAM-based FPGAs are highly complex devices, comprising millions of gates and several megabits of embedded memory. In such devices, two essential pieces of information are stored in SRAM cells: the user application state, and the configuration of routing elements and internal logic resources, which ultimately define the implemented hardware design. Consequently, a failure in any given cell could cause either application data or the hardware design to be altered, leading to a system malfunction. Designers of aerospace, safety-critical or military applications have since long faced such hazards; however, due to the shrinking geometry, reduced supply voltages and higher operating speeds of today's integrated circuits, it is predicted that in the near future even regular commercial designs will be required to cope with unreliable devices.
The book comprises ten short chapters, structured in a ‘bottom-up’ sequence of subjects ranging from the physical causes of failures to high-level protective design techniques. Following a brief introduction in Chapter 1, Chapter 2 starts with a detailed explanation on the physical causes of SRAM cells upsets. A single charged particle of radiation can displace thousands of electrons, causing electronic noise, signal spikes, and in digital circuits, clearly incorrect results. A particularly susceptible node is the drain of an off-state transistor; when hit by a particle, the energy transfer can cause the transistor to switch on, reversing the value stored in the cell. This phenomenon is called a bit-flip, or a single event upset (SEU).
