Efficient DSP Architecture for Viterbi Decoding with Small Trace Back Latency

Weon Heum PARK
Myung Hoon SUNWOO
Seong Keun OH

Publication
IEICE TRANSACTIONS on Communications   Vol.E89-B    No.10    pp.2813-2818
Publication Date: 2006/10/01
Online ISSN: 1745-1345
DOI: 10.1093/ietcom/e89-b.10.2813
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Fundamental Theories for Communications
Keyword: 
Viterbi algorithm,  DSP,  trace back,  instruction,  VLSI architecture,  wireless communication,  

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Summary: 
This paper proposes efficient DSP instructions and their hardware architecture for the Viterbi algorithm. The implementation of the Viterbi algorithm on a DSP chip has been attracting more interest for its flexibility, programmability, etc. The proposed architecture can reduce the Trace Back (TB) latency and can support various wireless communication standards. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for acceleration of the trellis butterfly computations. When the constraint length K is 5, the proposed architecture can reduce the decoding cycles about 17% compared with Carmel DSP and about 45% compared with TMS320C55x.