IEICE Trans - Asynchronous Multiple-Issue On-Chip Bus with In-Order/Out-of-Order Completion

Asynchronous Multiple-Issue On-Chip Bus with In-Order/Out-of-Order Completion

Eun-Gu JUNG
Jeong-Gun LEE
Sang-Hoon KWAK
Kyoung-Son JHANG
Jeong-A LEE
Dong-Soo HAR

Publication
IEICE TRANSACTIONS on Electronics Vol.E88-C No.12 pp.2395-2399
Publication Date: 2005/12/01
Online ISSN:
DOI: 10.1093/ietele/e88-c.12.2395
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Integrated Electronics
Keyword:
GALS, asynchronous on-chip bus, distributed control, multiple-issue,

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Summary:
A multiple-issue on-chip bus of a layered architecture in a Globally Asynchronous Locally Synchronous (GALS) design style, supporting in-order/out-of-order completion, is proposed in this letter. The throughput of the proposed on-chip bus is increased by 31.3% and 34.3%, while power consumption overhead is only 6.76% and 3.98%, respectively, as compared to an asynchronous single-issue on-chip bus.