IEICE Trans - MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process

MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process

Ming-Dou KER
Kun-Hsien LIN
Che-Hao CHUANG

Publication
IEICE TRANSACTIONS on Electronics Vol.E88-C No.3 pp.429-436
Publication Date: 2005/03/01
Online ISSN:
DOI: 10.1093/ietele/e88-c.3.429
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword:
electrostatic discharge (ESD), diode, poly-bounded diode, MOS-bounded diode, ESD protection,

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Summary:
New diode structures without the field-oxide boundary across the p/n junction for ESD protection are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the field oxide isolation across the p/n junction in the diode structure. The proposed N(P)MOS-bounded diodes can provide more efficient ESD protection to the internal circuits, as compared to the other diode structures. The N(P)MOS-bounded diodes can be used in the I/O ESD protection circuits, power-rail ESD clamp circuits, and the ESD conduction cells between the separated power lines. From the experimental results, the human-body-model ESD level of ESD protection circuit with the proposed N(P)MOS-bounded diodes is greater than 8 kV in a 0.35-µm CMOS process.