IEICE Trans - Low-Power Design of High-Speed A/D Converters

Low-Power Design of High-Speed A/D Converters

Shoji KAWAHITO
Kazutaka HONDA
Masanori FURUTA
Nobuhiro KAWAI
Daisuke MIYAZAKI

Publication
IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.468-478
Publication Date: 2005/04/01
Online ISSN:
DOI: 10.1093/ietele/e88-c.4.468
Print ISSN: 0916-8516
Type of Manuscript: Special Section INVITED PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category:
Keyword:
pipeline ADC, parallel-pipeline ADC, low-power design, power optimization,

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Summary:
In this paper, low-power design techniques of high-speed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A systematic approach to the power optimization of pipeline and parallel pipeline ADC's is introduced based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC. Finally, the theoretical minimum of required power as functions of the sampling rate, resolution and SNR is discussed. The analysis shows that, with the developments of new circuits and systems to approach to the minimum, the power can be further reduced by a factor of more than 1/10 without changing the basic architectures.