IEICE Trans - Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications

Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications

Kouji TSUNODA
Akira SATO
Hiroko TASHIRO
Toshiro NAKANISHI
Hitoshi TANAKA

Publication
IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.608-613
Publication Date: 2005/04/01
Online ISSN:
DOI: 10.1093/ietele/e88-c.4.608
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword:
system-on-a-chip, embedded RAM, direct tunneling, tunnel oxide, gate depletion,

Full Text: PDF(704.3KB)>>

Summary:
A direct tunneling memory (DTM) with ultra-thin tunnel oxide and depleted floating gate has been proposed for low power embedded RAM. To achieve excellent charge retention characteristics with ultra-thin tunnel oxide, floating gate depletion is adopted to utilize the band bending at the interface between floating gate and tunnel oxide in charge retention period. The depleted floating gate is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. These effects were evaluated by the device and process simulations and confirmed by the experimental data. As a consequence, both fast programming time and superior retention time have been achieved, which is a promising performance as a low power embedded RAM for system-on-a-chip (SoC) applications.