Thermally Robust Nickel Silicide Process for Nano-Scale CMOS Technology

Soon-Young OH
Jang-Gn YUN
Bin-Feng HUANG
Yong-Jin KIM
Hee-Hwan JI
Sang-Bum HUH
Han-Seob CHA
Ui-Sik KIM
Jin-Suk WANG
Hi-Deok LEE

Publication
IEICE TRANSACTIONS on Electronics   Vol.E88-C    No.4    pp.651-655
Publication Date: 2005/04/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.4.651
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamental and Application of Advanced Semiconductor Devices)
Category: Si Devices and Processes
Keyword: 
Ni-silicide,  bi-layer capping,  ternary phase,  nano-scale MOSFET,  

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Summary: 
A novel NiSi technology with bi-layer Co/TiN structure as a capping layer is proposed for the highly thermal immune Ni Silicide technology. Much better thermal immunity of Ni Silicide was certified up to 700, 30 min post silicidation furnace annealing by introducing Co/TiN bi-layer capping. The proposed structure is successfully applied to nano-scale CMOSFET with a gate length of 80 nm. The sheet resistance of nano-scale gate poly shows little degradation even after the high temperature furnace annealing of 650, 30 min. The Ni/Co/TiN structure is very promising for the nano-scale MOSFET technology which needs the ultra shallow junction and high temperature post silicidation processes