IEICE Trans - An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications

An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications

Jang-Jin NAM
Hong-June PARK

Publication
IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.773-777
Publication Date: 2005/04/01
Online ISSN:
DOI: 10.1093/ietele/e88-c.4.773
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
Keyword:
duty cycle correction, all-digital, multi-phase clock, PLL/DLL,

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Summary:
An all-digital CMOS duty cycle correction (DCC) circuit with a fixed rising edge was proposed to achieve the wide correction ranges of input duty cycle and PVT variations, the low standby power and the fast recovery from the standby mode for use in multi-phase clock systems. SPICE simulations showed that this DCC adjusts the output duty cycle to 50

0.7% for the wide range of input duty cycle from 15% to 85% at the input frequency of 1 GHz, within the commercial range of PVT corners. The all-digital implementation and the use of a toggle flip flop at the input stage enabled the wide correction ranges of PVT variations and input duty cycle, respectively.