A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC

Hideyuki NODA
Katsumi DOSAKA
Hans Jurgen MATTAUSCH
Tetsushi KOIDE
Fukashi MORISHITA
Kazutami ARIMOTO

Publication
IEICE TRANSACTIONS on Electronics   Vol.E89-C    No.11    pp.1612-1619
Publication Date: 2006/11/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.11.1612
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
soft error,  ECC,  TCAM,  embedded,  DRAM,  

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Summary: 
This paper describes a novel TCAM architecture designed for enhancing the soft-error immunity. An associated embedded DRAM and ECC circuits are placed next to TCAM macro to implement a unique methodology of recovering upset bits due to soft errors. The proposed configuration allows an improvement of soft-error immunity by 6 orders of magnitude compared with the conventional TCAM. We also propose a novel testing methodology of the soft-error rate with a fast parallel multi-bit test. In addition, the proposed architecture resolves the critical problem of the look-up table maintenance of TCAM. The design techniques reported in this paper are especially attractive for realizing soft-error immune, high-performance TCAM chips.