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Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology
Kenichi OHHATA Katsuyoshi HARASAWA Makoto HONDA Kiichi YAMASHITA
Publication
IEICE TRANSACTIONS on Electronics
Vol.E89-C
No.2
pp.203-205 Publication Date: 2006/02/01 Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.2.203 Print ISSN: 0916-8516 Type of Manuscript: LETTER Category: Microwaves, Millimeter-Waves Keyword: VCO, CMOS, 10 GHz,
Full Text: PDF(180.7KB)>>
Summary:
A low-noise, low-power 10-GHz CMOS VCO was developed using cost-effective 0.18-µm CMOS technology. A complementary cross-coupled topology was employed to decrease the power dissipation and phase noise. The fabricated VCO demonstrates a low phase noise of -106 dBc/Hz at an offset frequency of 1 MHz and a low power dissipation of 4.4 mW.
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