IEICE Trans - Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect

Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect

Yoichi YUYAMA
Akira TSUCHIYA
Kazutoshi KOBAYASHI
Hidetoshi ONODERA

Publication
IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.327-333
Publication Date: 2006/03/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.3.327
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Interface and Interconnect Techniques
Keyword:
alternate self shielding, on-chip global interconnect, critical transition and bus encoding,

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Summary:
In this paper, we propose alternate self shielding to remove critical transitions of on-chip global interconnect. Our proposed method alternates shield and signal wires cycle by cycle. The conventional self-shielding methods need additional wires to remove critical transition by encoding. The proposed alternate self-shielding, however, requires no additional wires. We evaluate our method by simulating signal transimission with a circuit simulator. As a result, our proposed method is superior in bit rate compared to others from 10% to 75%.