IEICE Trans - Trends of On-Chip Interconnects in Deep Sub-Micron VLSI

Trends of On-Chip Interconnects in Deep Sub-Micron VLSI

Danardono Dwi ANTONO
Kenichi INAGAKI
Hiroshi KAWAGUCHI
Takayasu SAKURAI

Publication
IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.392-394
Publication Date: 2006/03/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.3.392
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Interconnect Technique
Keyword:
on-chip interconnects, deep sub-micron, inductive effect, signal integrity,

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Summary:
This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions.