IEICE Trans - Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits

Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits

Zheng LIU
Masanori FURUTA
Shoji KAWAHITO

Publication
IEICE TRANSACTIONS on Electronics Vol.E89-C No.6 pp.710-716
Publication Date: 2006/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.6.710
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category:
Keyword:
RC mismatch, clock skew, time-interleaved ADCs, compensation, sampling clock phase calibration,

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Summary:
The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. The paper points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew compensation. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15 dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency. This paper also proposes a method of clock skew and RC mismatch compensation in time-interleaved sample-and-hold (S/H) circuits by sampling clock phase adjusting.