IEICE Trans - All-Digital Clock Deskew Buffer with Variable Duty Cycles

All-Digital Clock Deskew Buffer with Variable Duty Cycles

Shao-Ku KAO
Shen-Iuan LIU

Publication
IEICE TRANSACTIONS on Electronics Vol.E89-C No.6 pp.753-760
Publication Date: 2006/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.6.753
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category:
Keyword:
skew, duty cycle, pulsewidth detector, time-to-digital conversion,

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Summary:
An all-digital clock deskew buffer with variable duty cycles is presented. The proposed circuit aligns the input and output clocks with two cycles. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle. The output clock with adjustable duty cycles can be generated. The proposed circuit has been fabricated in a 0.35 µm CMOS technology. The measured duty cycle of the output clock can be adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 MHz to 600 MHz.