Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards

Yong-Ju KIM; Won-Young JUNG; Jae-Kyung WEE

Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards

Yong-Ju KIM
Won-Young JUNG
Jae-Kyung WEE

Publication
IEICE TRANSACTIONS on Electronics Vol.E89-C No.7 pp.1097-1105
Publication Date: 2006/07/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.7.1097
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword:
partial equivalent electrical circuit (PEEC), power distribution network (PDN), path-based equivalent circuit (PBEC),

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Summary:
Fast and accurate power bus designer (FAPUD) for multi-layers high-speed digital boards is the power supply network design tool for accurate and precise high speed board. FAPUD is constructed based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching in can be carried out because the I/O switching effect on a power supply noise can estimate for the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.