Simulation Study of a Novel Collector-up npn InGaP/GaAs Heterojunction Bipolar Transistor with a p-Type Doping Buried Layer for Current Confinement

Hung-tsao HSU
Yue-ming HSIN

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.1    pp.171-178
Publication Date: 2007/01/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.1.171
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword: 
C-up HBT,  doping buried layer,  

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Summary: 
In this paper, we report a new collector-up npn heterojunction bipolar transistor (C-up HBT) which employs a p-type doping buried layer inserted between extrinsic emitter and subemitter for current confinement. A theoretical study is performed to verify the functionality of the p-type doping buried layer using a two-dimensional device simulator. The structural parameters of the device and bias conditions on the buried layer are investigated to understand the limitations and the potential of devices. It is found that the emitter structure should be optimized to achieve the high efficiency of current confinement and the design of overlap between base-collector junction and buried layer is effective to suppress the carrier-blocking effect. Moreover, proposed C-up HBT demonstrates the similar current-gain cutoff frequency (fT) characteristics compared with conventional C-up HBT fabricated by ion implantations. The impact of fT caused by the external base-emitter capacitance (CBE,ext) can be relieved by further structural optimization of the emitter layer and lateral scaling of the extrinsic region. To clarify the feasibility of the proposed C-up HBTs, we also specify the fabrication process for the devices with epitaxial regrowth techniques.