IEICE Trans - CMOS Imaging Devices for New Markets of Vision Systems

CMOS Imaging Devices for New Markets of Vision Systems

Shoji KAWAHITO

Publication
IEICE TRANSACTIONS on Electronics Vol.E90-C No.10 pp.1858-1868
Publication Date: 2007/10/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.10.1858
Print ISSN: 0916-8516
Type of Manuscript: Special Section INVITED PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category:
Keyword:
CMOS image sensor, pinned photodiode, noise reduction, on-chip image processing, A/D conversion,

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Summary:
This paper reviews and discusses devices, circuits, and signal processing techniques for CMOS imaging SoC's based on column-parallel processing architecture. The pinned photodiode technology improves the noise characteristics at the device level to be comparable to CCD image sensors and as a result, low-noise design in CMOS image sensors has been shifted to the reduction of noise at the circuit level. Techniques for reducing the circuit noise are discussed. The performance of the imaging SoC's greatly depends on that of the analog-to-digital converter (ADC) used at the column. Three possible architectures of the column-parallel ADC are reviewed and their advantage and disadvantage are discussed. Finally, a few applications of the device and circuit techniques and the column-parallel processing architecture are described.