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11-Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic
Sun Hong AHN Jeong Beom KIM
Publication
IEICE TRANSACTIONS on Electronics
Vol.E90-C
No.3
pp.623-627 Publication Date: 2007/03/01 Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.3.623 Print ISSN: 0916-8516 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: redundant multi-valued logic, multi-valued logic, demultiplexer, high-speed interface circuit,
Full Text: PDF(991.1KB)>>
Summary:
This paper describes an 11-Gb/s CMOS demultiplexer (DEMUX) using redundant multi-valued logic (RMVL). The proposed circuit is received to serial binary data and is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented DEMUX consists of eight integrators. The DEMUX is designed with 0.35 µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The DEMUX is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43 mW. This circuit is expected to operate at higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.
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