IEICE Trans - Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS

Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS

Kazutami ARIMOTO
Toshihiro HATTORI
Hidehiro TAKATA
Atsushi HASEGAWA
Toru SHIMIZU

Publication
IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.657-665
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.657
Print ISSN: 0916-8516
Type of Manuscript: Special Section INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category:
Keyword:
low power, power management, DSP, SIMD,

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Summary:
Many embedded system application in ubiquitous network strongly require the high performance SoC with overcoming the physical limitations in the advanced CMOS. To develop these SoC, the continuous design efforts have been done. The initial efforts are the primitive level circuit technique and power switching control method for suppressing the standby currents. However, the additional physical limitations and system enhancements becomes main factors, the new design efforts have been proposed. These design efforts are the application-oriented technologies from the system level to device level. This paper introduces the self voltage controlled technique to cancel the PVT (process, voltage, and temperature) variation, power distribution and power management for cellular phone application, parallel algorithm and optimized layout DSP, and massively parallel fine-grained SIMD processor for next multimedia application. The high performance SoC for the embedded are achieved by providing the components of the system level IPs and making the application oriented SoC platform.