Cooperative Cache System: A Low Power Cache System for Embedded Processors

Gi-Ho PARK
Kil-Whan LEE
Tack-Don HAN
Shin-Dug KIM

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.4    pp.708-717
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.708
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
low power cache,  cooperative cache,  block size,  associativity,  embedded processor,  

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Summary: 
This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25 µm 4-metal process technology.