IEICE Trans - An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors

An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors

Koichi ISHIDA
Atit TAMTRAKARN
Hiroki ISHIKURO
Makoto TAKAMIYA
Takayasu SAKURAI

Publication
IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.786-792
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.786
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Analog and Communications
Keyword:
outside-rail, opamp, scaling,

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Summary:
An opamp design with outside-rail output relaxing a low-voltage constraint on future scaled transistors is presented. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8-V 0.18-µm standard CMOS process. The 3-V-output operation is experimentally verified. The outside-rail output design with scaled transistors shows area advantage over un-scaled and inside-rail design while keeping signal-to-noise ratio and gain bandwidth constant. The chip area is estimated to be 47% of the conventional opamp using a 0.35-µm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-µm CMOS design due to reduced capacitor area. The proposed design could be extended to n-tuple V_DD operation and applied to circuits with a feed back loop such as gain stage and filters. The extendibility of n-tuple V_DD operation and its application are discussed with simulation results.