IEICE Trans - An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator

Young-Chan JANG
Jun-Hyun BAE
Sang-Hune PARK
Jae-Yoon SIM
Hong-June PARK

Publication
IEICE TRANSACTIONS on Electronics Vol.E90-C No.6 pp.1156-1164
Publication Date: 2007/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.6.1156
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category:
Keyword:
flash ADC, time-interleaving, phase-locked-loop, digital phase adjuster, digital duty cycle corrector,

Full Text: PDF(1.5MB)>>

Summary:
An 8.8-GS/s 6-bit CMOS analog-to-digital converter (ADC) chip was implemented by time-interleaving eight 1.1-GS/s 6-bit flash ADCs with a 0.18-µm CMOS process. Eight uniformly-spaced 1.1 GHz clocks with 50% duty cycle for the eight flash ADCs were generated by a clock generator, which consists of a phase-locked-loop, digital phase adjusters and digital duty cycle correctors. The input bandwidth of ADC with the ENOB larger than 5.0 bits was measured to be 1.2 GHz. The chip area and power consumption were 2.24 mm² and 1.6 W, respectively.