Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements

Kouji ICHIKAWA
Yuki TAKAHASHI
Makoto NAGATA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.6    pp.1282-1290
Publication Date: 2007/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.6.1282
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
large scale integration,  electro magnetic interference,  printed circuit board,  signal integrity,  power supply integrity,  integrated analysis,  

Full Text: PDF(2.3MB)>>
Buy this Article


Summary: 
Power supply noise waveforms are acquired in a voltage domain by an on-chip monitor at resolutions of 0.3 ns/1.2 mV, in a digital test circuit consisting of 0.18-µm CMOS standard logic cells. Concurrently, magnetic field variation on a printed circuit board (PCB) due to power supply current of the test circuit is measured by an off-chip magnetic probing technique. An equivalent circuit model that unifies on- and off-chip impedance network of the entire test setup for EMI analysis is used for calculating the on-chip voltage-mode power supply noise from the off-chip magnetic field measurements. We have confirmed excellent consistency in frequency components of power supply noises up to 300 MHz among those derived by the on-chip direct sensing and the off-chip magnetic probing techniques. These results not only validate the state-of-the art EMI analysis methodology but also promise its connectivity with on-chip power supply integrity analysis at the integrated circuit level, for the first time in both technical fields.