Digitally Controlled Duty Cycle Corrector with 1 ps Resolution

Youngkwon JO
Hoyoung PARK
Sanghyuk YANG
Suki KIM
Kwang-Hyun BAEK

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.9    pp.1841-1843
Publication Date: 2007/09/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.9.1841
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
Keyword: 
duty cycle corrector,  variable delay unit,  delay locked loop,  

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Summary: 
This letter describes a digitally controlled duty cycle corrector (DCC) with 1 ps resolution. A new half period delay line (HPDL) control scheme using a delay locked loop (DLL) is proposed. The DCC has an output duty error less than 0.5% for 25% input duty error and operates correctly from 200 MHz to 800 MHz in a 0.18 µm CMOS technology.