This work describes a 12b 200kS/s 0.52mA 0.47mm² ADC for sensor applications such as motor control, 3-phase power control, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with a recycling signal path to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels employs a folded-cascode amplifier to achieve a required DC gain and a high phase margin. A 3-D fully symmetric layout with critical signal lines shielded reduces the capacitor and device mismatch of the multiplying D/A converter while switched-bias power-reduction circuits minimize the power consumption of analog amplifiers. Current and voltage references are integrated on chip with optional off-chip voltage references for low glitch noise. The down-sampling clock signal selects the sampling rate of 200kS/s and 10kS/s with a further reduced power depending on applications. The prototype ADC in a 0.18μm n-well 1P6M CMOS process demonstrates a maximum measured DNL and INL within 0.40 LSB and 1.97 LSB and shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200kS/s, respectively. The ADC occupies an active die area of 0.47mm² and consumes 0.94mW at 200kS/s and 0.63mW at 10kS/s with a 1.8V supply.