Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)

Seongjae CHO; Han PARK; Jung Hoon LEE; Jang-Gn YUN; Doo-Hyun KIM; Jong Duk LEE; Hyungcheol SHIN; Byung-Gook PARK

doi:10.1093/ietele/e91-c.5.731

Special Section on Fundamentals and Applications of Advanced Semiconductor Devices

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)

Seongjae CHO, Han PARK, Jung Hoon LEE, Jang-Gn YUN, Doo-Hyun KIM, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK

Author information

Seongjae CHO
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
The Institute of Electronics, Information and Communication Engineers
Han PARK
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Jung Hoon LEE
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Jang-Gn YUN
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Doo-Hyun KIM
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Jong Duk LEE
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Hyungcheol SHIN
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University
Byung-Gook PARK
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University

Keywords: memory array, electrical interference, 3-D memory device, read operation, PCI (paired cell interference)

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2008 Volume E91.C Issue 5 Pages 731-735

DOI https://doi.org/10.1093/ietele/e91-c.5.731

Details

Abstract

Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.

Corresponding author

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